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Preliminary Technical Data
FEATURES
Dual-axis impact sensing Dual-axis acceleration sensing, +70g, +35g 14-bit resolution 17.1 mg/LSB, 8.55mg/LSB sensitivity Impact peak-level sample and hold Programmable Event Recorder 400Hz double-pole Bessel sensor response 12-bit digital temperature sensor output Digitally controlled sensitivity and bias Digitally controlled sample rate, up to 4096 SPS Dual alarm settings with programmable threshold limits Auxiliary digital I/O Digitally activated self test Digitally activated low power mode SPI(R)-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: 3.0 V to +3.6 V 3500 g powered shock survivability
Programmable Dual Axis Digital Accelerometer and Impact Sensor ADIS16204
FUNCTIONAL BLOCK DIAGRAM
AUX AUX ADC DAC VREF
Temperature Sensor Inertial MEMS Sensor
Signal Conditioning & Conversion
Digital Processing SPI Port Digital Control
CS SCLK DIN DOUT
Self-Test
VDD
Power Management
Alarms
Aux I/O
COM RST DIO0 DIO1
Figure 1.
APPLICATIONS
Impact detection Condition monitoring Safety Systems Shock sensor
GENERAL DESCRIPTION
The ADIS16204 is a programmable impact sensor in a single compact package enabled by the Analog Devices iSensorTM integration. By enhancing the Analog Devices iMEMS(R) sensor technology with an embedded signal processing solution, the ADIS16204 provides tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI interface provides access to measurements for dual-axis linear acceleration, a root-sum-square (RSS) of both axes, temperature, power supply, and one auxiliary analog input. Easy access to digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system offset calibration, along with convenient sample rate control. The ADIS16204 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface: * * * * * * Peak sample and hold Programmable Event Recording Configurable trigger levels Auxiliary 12-bit ADC and DAC Configurable digital I/O port Digital self-test function
The ADIS16204 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16204 is available in a 9.2 mm x 9.2 mm x 3.9 mm laminate-based land grid array (LGA) package with a temperature range of -40C to +105C.
Rev. PrA
10/10/2006 4:24 AM One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Preliminary Technical Data TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5
ADIS16204
Timing Diagrams ..........................................................................5 Absolute Maximum Ratings ............................................................6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 RECOMMENDED PAD GEOMETRY ..........................................7 Outline Dimensions ..........................................................................8 Ordering Guide .............................................................................8
REVISION HISTORY
8/06--Revision PSD1: PSD1 Kickoff Version
Rev. PrA | Page 2 of 9
Preliminary Technical Data SPECIFICATIONS
TA = -40oC to +105C, VDD = 3.3 V, unless otherwise noted. Table 1.
Parameter ACCELEROMETER Output Full-Scale Range Sensitivity Non linearity Sensor-to-sensor Alignment Error Cross-axis Sensitivity Resonant Frequency OFFSET Zero-g Output NOISE Noise Density Conditions Axis X Y X Y Min +70 +35 17.1 8.55 0.2 0.1 -5 24 +5 Typ Max
ADIS16204
Unit g g mg/LSB mg/LSB % Degrees % kHz
X Y 10Hz - 400Hz, no post filtering
0.2 1.85 1.8
g g mg/Hz
FREQUENCY RESPONSE Sensor Bandwidth (-3dB) Temperature Drift ACCELEROMETER SELF-TEST STATE1 Output Change When Active Output Change When Active TEMPERATURE SENSOR Output at 25C Scale Factor ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time
2-pole Bessel |25 - Tmin| or |Tmax - 25C| 25C X Y
360
400 2 585 1170 1278 -2.13 12 2 1 4 2
440
Hz Hz LSB LSB LSB LSB/C Bits LSB LSB LSB LSB V pF V mV ppm/oC Bits LSB LSB mV % V s
0 During acquisition At 25C -10 40 70 5 k/100 pF to GND For Code 101 to Code 4095 12 4 1 5 0.5 0 to 2.5 2 10 20 2.5
2.5
+10
Rev. PrA | Page 3 of 9
ADIS16204
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period2 FLASH MEMORY Endurance3 Data Retention4 CONVERSION RATE Minimum Conversion Time Maximum Conversion Time Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range VDD Power Supply Current Conditions Axis Min 2.0 VIH = VDD VIL = 0 V
Preliminary Technical Data
Typ Max Unit V V A A pF V V Seconds Cycles Years 244 484 4096 2.066 3.0 Normal mode, SMPL_TIME 0x08 (fs 910 Hz), at 25C Fast mode, SMPL_TIME 0x07 (fs 1024 Hz), at 25C Sleep mode, at 25C 3.3 12 37 mA 500 130 750 A ms 3.6 s ms SPS SPS V mA
0.2 -40 10 2.4
0.8 1 -60
ISOURCE = 1.6 mA ISINK = 1.6 mA
0.4 0.5 20,000 20 128
TJ = 85C
Turn-On Time
1 2
Self-test response changes as the square of VDD. Guaranteed by design. 3 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +105C.
4
Retention lifetime equivalent at junction temperature (TJ) 55C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
Rev. PrA | Page 4 of 9
Preliminary Technical Data
TIMING SPECIFICATIONS
TA = 25C, VDD = 3.3 V, tilt = 0, unless otherwise noted. Table 2.
Parameter fSCLK tDATARATE tDATARATE tcs tDAV tDSU tDHD tDF tDR tSFS
1
ADIS16204
Description Fast mode, SMPL_TIME 0x07 (fs 1024 Hz) Normal mode, SMPL_TIME 0x08 (fs 910 Hz) Chip select period, fast mode, SMPL_TIME 0x07 (fs 1024 Hz) Chip select period, normal mode, SMPL_TIME 0x08 (fs 910 Hz) Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge
Min1 0.01 0.01 40 100 48.8 24.4 48.8
Typ
Max 2.5 1.0
Unit MHz MHz s s ns ns ns ns ns min ns min ns typ
100
5 5 5
12.5 12.5
Guaranteed by design, not tested.
TIMING DIAGRAMS
tDATA RATE tSTALL
CS
tSTALL = tDATA RATE - 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
tCS
1 SCLK 2 3 4 5 6 15 16
05462-002
SCLK
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A5
tDHD
A4 A3 A2 D2 D1 LSB
05462-003
Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. PrA | Page 5 of 9
ADIS16204 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered) Acceleration (Any Axis, Powered) VDD to COM Digital Input/Output Voltage to COM Analog Inputs to COM Analog Inputs to COM Operating Temperature Range Storage Temperature Range Rating 3500 g 3500 g -0.3 V to +7.0 V -0.3 V to +5.5 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -40C to +125C -65C to +150C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Characteristics
Package Type 16-Terminal LGA JA 250C/W JC 25C/W Device Weight 0.6 grams
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 6 of 9
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COM VREF AUX ADC VDD 16 15 14 13
ADIS16204
SCLK
1
Y
12
AUX DAC
ADIS16204 DOUT 2
X
11 TOP VIEW (NOT TO SCALE)
N/C
DIN
3 N/C - DO NOT CONNECT
10
COM
CS
4
9
RST
5
6
7
8
DIO0
DIO1
N/C
COM
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6 7, 11 8, 10 9 12 13 14 15 16
1
Mnemonic SCLK DOUT DIN CS DIO0, DIO1 NC AUX COM RST AUX DAC VDD AUX ADC VREF COM
Type1 I O I I I/O - S I O S I O S
Description Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data to the control registers. Data Out. The data on this pin represents data being read from the control registers and is clocked out on the falling edge of the SCLK. Data In. Data written to the control registers is provided on this input and is clocked in on the rising edge of the SCLK. Chip Select, Active Low. This input frames the serial data transfer. Multifunction Digital I/O Pins. No Connect. Auxiliary Grounds. Connect to GND for proper operation. Reset, Active Low. This input resets the embedded microcontroller to a known state. Auxiliary DAC Analog Voltage Output. +3.3 V Power Supply. Auxiliary ADC Analog Input Voltage. Precision Reference Output. Common. Reference point for all circuitry in the ADIS16204.
S = Supply; O = Output; I = Input.
RECOMMENDED PAD GEOMETRY
1.178 BSC (8 PLCS) 0.670 BSC (12 PLCS)
7.873 BSC (2 PLCS) 1.127 BSC (16 PLCS)
05462-041
0.500 BSC (16 PLCS)
Figure 5. Example Pad Layout
Rev. PrA | Page 7 of 9
ADIS16204 OUTLINE DIMENSIONS
9.327 MAX SQ 1.405 BSC
13 12
Preliminary Technical Data
A1 CORNER INDEX AREA
16 1
0.797 BSC
1.00 BSC
9 8 5 4
TOP VIEW
BOTTOM VIEW
0.227 BSC (4 PLCS)
0.373 BSC (16 PLCS)
5.00 TYP
3.90 MAX
030906-A
SIDE VIEW
Figure 6. 16-Terminal Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16204BCCZ1 ADIS16204/PCBZ
1
Temperature Range -40C to +105C
Package Description 16-Terminal Land Grid Array [LGA] Evaluation Board
Package Option CC-16-2
Z = Pb-free part.
Rev. PrA | Page 8 of 9
Preliminary Technical Data
ADIS16204
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06448-0-10/06(PrA)
Rev. PrA | Page 9 of 9

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